Highly resistive polysilicon is essential for static RAMs with high packing density and low powder dissipation, but the high dopant diffusion coefficient in polysilicon grain boundary limits the minimum length of the polysilicon thin film resistor to be scaled down. In the coventional technique, as depicted by R. Sakto, et al in "A Novel Scaled Down Oxygen Implanted Polysilicon Resistor for Future Static RAMs" published in the 1986 IEEE International Electron Devices Meeting Proceedings, the scaling down of resistors can be realized by using oxygen as an implantation source. When oxygen is implanted into polysilicon layer, the dopant (such as arsenic) diffusing speed in the polysilicon grain boundary drastically decreases after high temperature treatment, as described by T. Ohzone et al in an article entitled, "Ion-Implanted Thin Polycrystalline Silicon High-Value Resistors for High Density Poly-Load Static RAM Applications", in the IEEE Transactions on Electron Device, Vol. ED-32, September 1985, pp. 1749-1755.
Nowadays, polysilicon thin film transistor has received a great deal of attention for its application for high packing density three-dimension integrated circuit, as described by T. Ohzone, et al in "An 8K.times.8 Bit Static MOS RAM Fabricated by n-MOS/n-well CMOS Technology" in the IEEE Journal of Solid State Circuits, Vol. SC-15. October 1980, pp. 854-861. For high packing density and high speed operation of three-dimension integrated circuits, the size of polysilicon thin film transistor must be scaled down and the threshold voltage must be kept as low as possible. The oxygen implantation method to scale down the size of polysilicon thin film resistor described by T. Ohzone cannot be used to scale down the size of polysilicon thin film transistor, because this method increases the threshold voltage of the polysilicon thin film transistor. As a result, additional lithographic processes are needed to mask the transistor region while implanting with oxygen the resistor region on the polysilicon thin film.